1. Technical Field
The present invention relates to a substrate, a method for fabricating a substrate, a semiconductor device, and a method for fabricating a semiconductor device.
2. Related Art
Semiconductor packages are roughly classified into peripheral type packages and area type packages. A peripheral type package is a package in which the external terminals are arranged on the periphery of the package, and an area type package is a package in which the external terminals are arranged on the lower surface of the package. FIGS. 20A through 20C show typical peripheral type packages called a dual in-line package (DIP), a small out-line package (SOP), and a quad flat package (QFP). The peripheral type package, as shown in FIG. 20D, includes an integrated circuit (IC) element 210 mounted on a chip-mounting section called a die pad 201. Electrodes on the IC element 210 and leads 203 of a lead frame are coupled by e.g. gold wires. Then, these elements, not including peripheral portions of the leads 203, are sealed with resin. Portions of the leads 203 inside the resin package are called internal terminals, and portions of the leads 203 outside the resin package are called external terminals.
The area type package, with reference to FIGS. 21A and 21B and FIGS. 22A and 22B, is a package represented by a ball grid array (BGA) package which is fabricated by mounting the IC element 210 on a substrate 211, electrically coupling the IC element 210 to the substrate 211 with either gold wires, solder, or gold bumps, and sealing the elements such as the IC element 210 with resin. Referring to FIGS. 21A and 21B, the package in which the substrate 211 is coupled to the IC element 210 with gold wires 213 is called a gold wire BGA package.
Also, a package with reference to FIGS. 22A and 22B is called a bump BGA package in which the substrate 211 is coupled to the IC element 210 with bumps 223. FIGS. 22A and 22B, in particular, show a type of bump BGA that is not sealed with resin. As shown in FIGS. 21A through 22B, the external terminals of the area type are not the leads but electrodes 225 (or solder balls 19) mounted on the rear surface of the substrate 211.
Manufactured also in recent years is a package, with reference to FIGS. 23A through 23I, which is fabricated by: electroplating columnar-shaped terminals 233 and an columnar-shaped die pad 235 on a metal plate 231, mounting the IC element 210 on the die pad 235, coupling the IC element 210 to the terminals 233 with the gold wires 213, conducting resin sealing, peeling off the metal plate 231 from a resin-formed portion 236, and dicing into each separate product.
More specifically, with reference to FIGS. 23A and 2313, a resist is first coated on the metal plate 231, and the coated metal plate 231 is subjected to exposure and development to form a resist pattern 237. Then, referring to FIG. 23C, copper or the like is electroplated on the surface of the metal plate 231 that is exposed at the lower part of the resist pattern 237 so as to form the columnar shaped terminals 233 and die pad 235. Thereafter, referring to FIG. 23D, the resist pattern is removed. Then, with reference to FIG. 23E, the IC element 210 is mounted on the die pad 235 through electroplating, followed by wire bonding. Then, with reference to FIG. 23F, the IC element, gold wires 213, etc. are sealed with resin. Referring to FIG. 23G, the metal plate 231 is then peeled off from the resin-formed portion 236. Thereafter, referring to FIGS. 23H and 23I, the resin-formed portion 236 is diced into each separate product, and the package is thereby produced.
JP-A-2-240940 discloses a technique in which a peripheral type package is fabricated by: half-etching one surface of a support of a tabular lead frame, mounting an IC element on a die pad of the lead frame, conducting wire bonding and resin sealing, and thereafter removing the support by polishing the other surface of the support whose one surface has been half-etched, thereby fabricating the peripheral type package. Disclosed in JP-A-2004-281486 is a technique intended to enhance versatility of the area type package by radially arranging the wires from the center of the substrate to outside in plan view.
In the related art techniques, the peripheral type packages, the area type packages, the package referring FIGS. 23A through 23I, and the package described in JP-A-2-240940 all require a die pad as an IC element-mounting plane or a substrate such as an interposer. Therefore, depending on the size of the IC element and the number of external outputs from the IC element (i.e., the number of leads or balls), these packages need specific lead frames or specific substrates, or specific photomasks (to form the columnar shapes). In particular, in order to produce large item small volume products, a large number of lead frames or substrates or photomasks need be secured, and this has been a setback in reducing the production costs.
Also, in JP-A-2004-281486, an area type package that accommodates all chip sizes is accomplished by radially arranging the wires from the center of the substrate to outside. However, in this technology, it is necessary to arrange the pad terminals of the IC element so as to always overlap planarly with the wires that extend radially from the substrate center. Therefore, there is less degree of freedom of design in laying out the pad terminals. In other words, although the versatility of the package improves, restrictions placed on the IC element increases as well.